This application claims the benefit of Korean Patent Application No. 2000-53837, filed on Sep. 9, 2000 in Korea, which is hereby incorporated by reference.
1. Field of the Invention
This present invention relates to a thin film transistor (TFT), and more particularly, to a thin film transistor for an LCD device and a fabrication method thereof.
2. Description of the Related Art
In general, liquid crystal display (LCD) devices make use of optical anisotropy and polarization properties of liquid crystal molecules to control arrangement orientation. The arrangement direction of the liquid crystal molecules can be controlled by an applied electric field. Accordingly, when an electric field is applied to liquid crystal molecules, the arrangement of the liquid crystal molecules changes. Since refraction of incident light is determined by the arrangement of the liquid crystal molecules, display of image data can be controlled by changing the electric field applied to the liquid crystal molecules.
Of the different types of known LCDs, active matrix LCDs (AM-LCDs), which have thin film transistors and pixel electrodes arranged in a matrix form, are the subject of significant research and development because of their high resolution and superiority in displaying moving images.
FIG. 1 shows a typical LCD device. The LCD device 11 includes an upper substrate 5 and a lower substrate 22 with a liquid crystal layer 14 interposed therebetween. The upper substrate 5 and the lower substrate 22 are commonly referred to as a color filter substrate and an array substrate, respectively.
In the upper substrate 5 and upon the surface opposing the lower substrate 22, a black matrix 6 and a color filter layer 7 are formed in the shape of an array matrix and includes a plurality of red (R), green (G), and blue (B) color filters so that each color filter is surrounded by corresponding portions of the black matrix 6. Additionally, a common electrode 18 is formed on the upper substrate 5 that covers the color filter layer 7 and the black matrix 6. In the lower substrate 22 and upon the surface opposing the upper substrate 5, a thin film transistor (TFT) xe2x80x9cTxe2x80x9d is formed in the shape of an array matrix that corresponds to the color filter layer 7. A plurality of crossing gate lines 13 and data lines 15 are positioned such that each TFT xe2x80x9cTxe2x80x9d is located near each crossover point of the gate lines 13 and the data lines 15.
Furthermore, a plurality of pixel electrodes 17 are formed on a pixel region xe2x80x9cPxe2x80x9d that is defined by the gate lines 13 and the data lines 15 of the lower substrate 22. Each of the pixel electrodes 17 includes a transparent conductive material having good transmissivity such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO), for example.
According to the LCD device 11 of FIG. 1, a scanning signal is applied to a gate electrode of the TFT xe2x80x9cTxe2x80x9d through the gate line 13, while a data signal is applied to a source electrode of the TFT xe2x80x9cTxe2x80x9d through the data line 15. As a result, the liquid crystal molecules of the liquid crystal layer 14 are aligned and arranged by operation of the TFT xe2x80x9cTxe2x80x9d, and incident light passing through the liquid crystal layer 14 is controlled to display an image.
Within the configuration of the array substrate in the above-mentioned LCD device, an active channel is the most important part in the switching device (i.e., thin film transistor) operation. This active channel of the thin film transistor is usually made of polycrystalline silicon (poly-Si) or amorphous silicon (a-Si:H) having hydrogen.
Generally, the amorphous silicon (a-Si) is deposited on a glass substrate by thickness of 500 angstroms (xc3x85) using PECVD (plasma-enhanced chemical vapor deposition) or LPCVD (low pressure chemical vapor deposition). However, since the active channel constituted by this amorphous silicon is unstable compared to the polycrystalline silicon (poly-Si), a dangling bond occurs in a surface of the active channel. The dangling bond traps carrier electrons such that this dangling bond impedes the flow of carrier electons in the active channel, thus reducing conductivity. Accordingly, electron mobility in the amorphous silicon active channel is much less than that in the active channel constituted by the polycrystalline silicon. Namely, if the electron mobility of the active channel constituted by the amorphous silicon is 1 cm2/Vs, the electron mobility of the active channel constituted by the polycrystalline silicon is scores to hundreds cm2/Vs. Further, the electron mobility of a thin film transistor (TFT) employing the polycrystalline silicon as the active channel depends on the grain size of the polycrystalline silicon, defects existing in the grain boundary and interface defects between a gate insulating layer and a silicon layer. Namely, the larger the grain size; the larger the electron mobility. Also, the fewer defects that exist in the grain boundary and interface between the gate insulating layer and the silicon layer, the larger the electron mobility.
However, the poly-Si TFT has large OFF current because of a large electron mobility. The major reason for this phenomenon is that the leakage current increases in the border between doped and un-doped areas of the poly-Si. On the contrary, the amorphous silicon (a-Si) has smaller OFF current than the polycrystalline silicon (poly-Si).
Therefore, in a large-sized liquid crystal panel, the poly-Si element is generally arranged in the outer part of the liquid crystal panel and used as a driving device, while the a-Si element is used as a switching device. These uses are because the driving device needs high electron mobility and the switching device needs low OFF current in order to not affect the images of the liquid crystal panel. However, the switching device advisably needs both low OFF current and high electron mobility.
FIGS. 2A to 2E are cross-sectional views illustrating a fabrication process for a polycrystalline silicon (poly-Si) thin film transistor (TFT) using a conventional laser crystallization method.
Referring to FIG. 2A, a buffer layer 2 is formed on a substrate 22, and then an amorphous silicon (a-Si) layer 4 is deposited on the buffer layer 2. The buffer layer 2 is made of an insulating material and serves to prevent an alkali material from extracting from the substrate 22. After forming the amorphous silicon (a-Si), the crystallization process crystallizing the amorphous silicon layer 4 is performed using a laser beam. Thus, the a-Si is changed into poly-Si.
Thereafter, the polycrystalline silicon (poly-Si), as shown in FIG. 2B, is then patterned so as to form an active layer 9 in an island shape on the buffer layer 2.
Now, referring to FIG. 2C, a gate insulating layer 10 and a gate electrode 12 are formed on the island-shaped active layer 9. In order to reduce the mask processes, the gate insulating layer 10 and gate electrode 12 are simultaneously formed using the same mask. Since, the gate insulating layer 10 and the gate electrode 12 are disposed in the central portion of the active layer 9, the active layer 9 is divided into three areas, i.e., a first active area 16, a second active area 21 and a third active area 23. Accordingly, the gate insulation layer 10 and gate electrode 12 are on and over the second active area 21. The first and third active areas 16 and 23 are disposed on both sides of the active layer 9.
Thereafter, the active layer 9 is introduced by n+ (or p+) ion doping (plasma doping) using the gate electrode 12 as a mask. At this time, the gate electrode 12 acts as an ion-stopper that prevents the dopant (n+ or p+ ion) from penetrating into the second active area 21. Therefore, the second active area 21 remains as a pure silicon area, while the first and third active areas 16 and 23 doped by the dopant become impure silicon areas.
During the ion doping process, the electrical characteristics of the active layer 9 change depending on the dopant. If the dopant is a Group IIIA element gas such as B2H6 , the first and third active areas 16 and 23 become p-type semiconductor. Further, if the dopant is a Group VA element gas such as PH3, the first and third active areas 16 and 23 become n-type semiconductor. The dopant gases can be selected in accordance with the semiconductor type desired.
Now, referring to FIG. 2D, an interlayer insulator 25 is formed to cover the buffer layer 2, the first and third active areas 16 and 23, the gate insulating layer 10 and the gate electrode 12. Thereafter, first and second contact holes 17 and 24 are formed by patterning the inter layer insulator 25. The first and second contact holes 17 and 24 respectively expose portions of the first and third active areas 16 and 23.
Referring to FIG. 2E, source and drain electrodes 25 and 27 are formed by depositing and patterning a metallic material. The source electrode 25 contacts the first active area 16 through the first contact hole 17, while the drain electrode 27 contacts the third active area 23 through the second contact hole 24. After that, a passivation layer 26 is formed over the entire surface of the substrate 22. Then, a drain contact hole 29 to the drain electrode 27 is formed by patterning the passivation layer 26. Thus, the drain contact hole 29 exposes a portion of the drain electrode 27. Thereafter, a transparent conductive material is deposited on the passivation layer 26 and then patterned to form a pixel electrode 30 that contacts the drain electrode 27 through the drain contact hole 29. Accordingly, the poly-Si TFT is complete.
As mentioned above, the poly-Si TFT is fabricated using a conventional laser crystallization method such that the top gate coplanar type poly-Si TFT is fabricated. Namely, the TFT is a top-gate type.
When fabricating a TFT using poly-Si, the degradation of the electrical characteristics of the TFT still remains as one of the critical problems to be solved. In an area xe2x80x9cAxe2x80x9d near the drain junction, i.e., in a drain depletion region, the electron-hole pair generation easily occurs due to the trapped carriers existing in the grain and in the grain boundary of the poly-Si.
Accordingly, the display quality of the liquid crystal panel is deteriorated due to the large leakage current flow. Further, when driving the devices for a long time, the electrical characteristics of the elements is degraded. Namely, the atomic bond of silicon is broken or the dangling bond of silicon combining hydrogen (H) is broken. During the laser crystallization process, the laser beam cannot uniformly irradiate the substrate. If the laser beam irradiates the silicon layer more strongly, the thickness of the crystallized silicon is thicker. On the contrary, if the laser beam irradiates the amorphous silicon layer more lightly, the thickness of the crystallized silicon is thinner. Therefore, the characteristics of the TFT varies depending on whether the TFT is formed on the largely crystallized silicon or on the slightly crystallized silicon, thereby causing deterioration of the display device.
To overcome the problems described above, embodiments of the present invention provide a thin film transistor (and method of making the same) for use in a liquid crystal display device, which has a structure that provides high electron mobility, low OFF current, improved stability for a long time and uniform crystallization throughout a substrate.
The present invention, in part, provides a thin film transistor for use in a liquid crystal display device, the thin film transistor including: a substrate; a buffer layer on the substrate; a amorphous silicon layer having a pure amorphous silicon area and doped amorphous silicon areas, the pure amorphous silicon area having vertical offsets in both sides thereof, the doped amorphous silicon areas having source and drain areas, the doped amorphous silicon areas doped by a dopant, the source and drain areas positioned on both sides of the pure amorphous silicon area and etched to expose the vertical offsets; an oxidized layer on the pure amorphous silicon area; a polycrystalline silicon layer on the oxidized layer; a gate insulating layer on the polycrystalline silicon layer; a gate electrode on the gate insulating layer; an inter layer insulator having first and second contact holes, the inter layer insulator covering the amorphous silicon layer, the oxidized layer, the polycrystalline silicon layer, the gate insulating layer, and the gate electrode; and source and drain electrodes contacting the source areas through the first contact hole and the drain area through the second contact hole, respectively.
The amorphous silicon layer has a thickness of 3800-4200 angstroms (xc3x85), and the oxidized layer has a thickness of 10-20 angstroms (xc3x85). The oxidized layer is formed by dipping the substrate having the amorphous silicon layer into the solution that includes concentrated sulfuric acid and oxygenated water. The dopant is n+ or p+ ions.
The polycrystalline silicon layer has a thickness of 350-450 angstroms (xc3x85) and is formed by crystallizing the amorphous silicon using an excimer laser that has an energy level in a range of 220-270 mJ/cm2.
The present invention, also in part, provides methods of fabricating such thin film transistor for use in a liquid crystal display device. The methods include: forming a buffer layer on a substrate; forming a first amorphous silicon layer on the buffer layer; forming an oxidized layer on the amorphous silicon layer; forming a second amorphous silicon layer on the oxidized layer; crystallizing the second amorphous silicon layer to form a polycrystalline silicon layer; forming a gate insulating layer on the polycrystalline silicon layer; forming a gate electrode on the gate insulating layer; forming island-shaped gate electrode, gate insulating layer, polycrystalline silicon layer, and oxidized layer so as to expose the first amorphous silicon layer; forming source and drain areas by doping a dopant into the exposed first amorphous silicon layer using the island-shaped gate electrode as an ion stopper; forming an inter layer insulator having first and second contact holes, the inter layer insulator covering the amorphous silicon layer, the oxidized layer, the polycrystalline silicon layer, the gate insulating layer, and the gate electrode; and forming source and drain electrodes contacting the source areas through the first contact hole and the drain area through the second contact hole, respectively.
The first amorphous silicon layer has a thickness of 3800-4200 angstroms (xc3x85), and the oxidized layer has a thickness of 10-20 angstroms (xc3x85).
Forming the oxidized layer comprises dipping the substrate having the amorphous silicon layer into the solution that includes concentrated sulfuric acid and oxygenated water.
The dopant is n+ or p+ ions. The polycrystalline silicon layer has a thickness of 350-450 angstroms (xc3x85).
Crystallizing the second amorphous silicon layer uses an excimer laser that has an energy level in a range of 220-270 mJ/cm2.
Advantages of the present invention will become more apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.